H8SXSLASH1663M datasheet(165/1504 Pages) RENESAS

165 / 1504 page

Section 7 Interrupt Controller

Rev. 2.00 Sep. 24, 2008 Page 133 of 1468

REJ09B0412-0200

7.3.2

CPU Priority Control Register (CPUPCR)

CPUPCR sets whether or not the CPU has priority over the DTC, DMAC and EXDMAC. The

interrupt exception handling by the CPU can be given priority over that of the DTC, DMAC and

EXDMAC transfer. The priority level of the DTC is set by bits DTCP2 to DTCP0 in CPUPCR.

The priority level of the DMAC and EXDMAC is set by the DMAC and EXDMAC control

Bit

Bit Name

Initial Value

R/W

Note: * When the IPSETE bit is set to 1, the CPU priority is automatically updated, so these bits cannot be modified.

CPUPCE

R/W

DTCP2

R/W

DTCP1

R/W

DTCP0

R/W

IPSETE

R/W

CPUP2

R/(W)*

CPUP1

R/(W)*

CPUP0

R/(W)*

Bit

Bit Name

Initial

Value

R/W

Description

CPUPCE

R/W

CPU Priority Control Enable

Controls the CPU priority control function. Setting this bit

to 1 enables the CPU priority control over the DTC,

DMAC and EXDMAC.

0: CPU always has the lowest priority

1: CPU priority control enabled

DTCP2

DTCP1

DTCP0

R/W

DTC Priority Level 2 to 0

These bits set the DTC priority level.

000: Priority level 0 (lowest)

001: Priority level 1

010: Priority level 2

011: Priority level 3

100: Priority level 4

101: Priority level 5

110: Priority level 6

111: Priority level 7 (highest)

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