H8SXSLASH1663M datasheet(167/1504 Pages) RENESAS

167 / 1504 page

Section 7 Interrupt Controller

Rev. 2.00 Sep. 24, 2008 Page 135 of 1468

REJ09B0412-0200

7.3.3

Interrupt Priority Registers A to O, Q, and R

(IPRA to IPRO, IPRQ, and IPRR)

IPR sets priory (levels 7 to 0) for interrupts other than NMI.

Setting a value in the range from B'000 to B'111 in the 3-bit groups of bits 14 to 12, 10 to 8, 6 to 4,

and 2 to 0 assigns a priority level to the corresponding interrupt. For the correspondence between

the interrupt sources and the IPR settings, see table 7.2.

Bit

Bit Name

Initial Value

R/W



IPR14

R/W

IPR13

R/W

IPR12

R/W



IPR10

R/W

IPR9

R/W

IPR8

R/W

Bit

Bit Name

Initial Value

R/W



IPR6

R/W

IPR5

R/W

IPR4

R/W



IPR2

R/W

IPR1

R/W

IPR0

R/W

Bit

Bit Name

Initial

Value

R/W

Description



Reserved

This is a read-only bit and cannot be modified.

IPR14

IPR13

IPR12

R/W

Sets the priority level of the corresponding interrupt

source.

000: Priority level 0 (lowest)

001: Priority level 1

010: Priority level 2

011: Priority level 3

100: Priority level 4

101: Priority level 5

110: Priority level 6

111: Priority level 7 (highest)



Reserved

This is a read-only bit and cannot be modified.

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