H8SXSLASH1663M datasheet(276/1504 Pages) RENESAS

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Section 9 Bus Controller (BSC)

Rev. 2.00 Sep. 24, 2008 Page 244 of 1468

REJ09B0412-0200

9.6

Basic Bus Interface

The basic bus interface can be connected directly to the ROM and SRAM. The bus specifications

can be specified by the ABWCR, ASTCR, WTCRA, WTCRB, RDNCR, CSACR, and

ENDIANCR.

9.6.1

Data Bus

Data sizes for the CPU and other internal bus masters are byte, word, and longword. The bus

controller has a data alignment function, and controls whether the upper byte data bus (D15 to D8)

or lower byte data bus (D7 to D0) is used according to the bus specifications for the area being

accessed (8-bit access space or 16-bit access space), the data size, and endian format when

accessing external address space,. For details, see section 9.5.6, Endian and Data Alignment.

9.6.2

I/O Pins Used for Basic Bus Interface

Table 9.15 shows the pins used for basic bus interface.

Table 9.15

I/O Pins for Basic Bus Interface

Name

Symbol

I/O

Function

Bus cycle start

Output

Signal indicating that the bus cycle has started

Address strobe

AS*

Output

Strobe signal indicating that an address output on the

address bus is valid during access

Read strobe

Output

Strobe signal indicating the read access

Read/write

RD/

Output

Signal indicating the data bus input or output

direction

Low-high write

LHWR

Output

Strobe signal indicating that the upper byte (D15 to

D8) is valid during write access

Low-low write

LLWR

Output

Strobe signal indicating that the lower byte (D7 to

D0) is valid during write access

Chip select 0 to 7

CS0 to CS7 Output

Strobe signal indicating that the area is selected

Wait

WAIT

Input

Wait request signal used when an external address

space is accessed

Note:

When the address/data multiplexed I/O is selected, this pin only functions as the

output and does not function as the

AS output.

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