M32CSLASH86 datasheet(383/505 Pages) RENESAS

383 / 505 page

Page 360

23. CAN Module

)

(

23.3 Timing with CAN-Associated Registers

23.3.1 CAN Module Reset Timing

Figure 23.37 shows an operation example of when the CAN module is reset.

(1) The CAN module can be reset when the STATE_RESET bit in the CiSTR register (i=0,1) is set to "1"

(CAN module reset completed) after the RESET1 and RESET0 bits in the CiCTLR0 register are set to

"1" (CAN module reset).

(2) Set necessary CAN-associated registers.

(3) CAN communication can be established after the STATE_RESET bit is set to "0" (resetting) after

the RESET1 and RESET0 bits are set to "0" (CAN module reset exited) .

Figure 23.37 Example of CAN Module Reset Operation

23.3.2 CAN Transmit Timing

Figure 23.38 shows an operation example of when the CAN transmits a frame.

(1) When the TRMREQ bit in the CiMCTLj register (j=0 to 15) is set to "1" (request to transmit the data

frame) while the CAN bus is in an idle state, the TRMACTIVE bit in the CiMCTLj register is set to

"1" (during transmission) and the TRMSTATE bit in the CiSTR register is set to "1" (during trans-

mission). The CAN starts transmitting the frame.

(2) After a CAN frame transmission is completed, the SENTDATA bit in the CiMCTLj register is set to "1"

(already transmitted), the TRMSUCC bit in the CiSTR register to "1" (transmission completed) and the

SISj bit in the CiSISTR register to "1" (interrupt requested). The MBOX3 to MBOX0 bits in the CiSTR

RESET0 bit

"1"

"0"

RESET1 bit

"1"

"0"

STATE_RESET bit

"1"

"0"

Initial Setting for the CAN

Module

Verify the STATE_RESET bit

CAN Operation

Set to "1" by program

simultaneously

Operation (1)

Set to "0" by program

simultaneously

Operation (2)

Operation (3)

Verify the STATE_RESET bit

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