M32CSLASH86 datasheet(385/505 Pages) RENESAS

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Page 362

23. CAN Module

)

(

(1)

STATE_BUSERROR

bit

CAN bus

Error frame

Transmit / receive frame

BEIS bit

Error detected

"1"

"0"

"1"

"0"

23.3.4 CAN Bus Error Timing

Figure 23.40 shows an operation example of when a CAN bus error occurs.

(1) When a CAN bus error is detected, the STATE_BUSERROR bit in the CiSTR register is set to "1",

(error occurred) and the BEIS bit in the CiEISTR register is set to "1" (interrupt requested). The

CAN starts transmitting the error frame.

Figure 23.40 Operation Timing when CAN Bus Error Occurs

23.4 CAN Interrupts

The CAN1 wake-up interrupt and CANij interrupts (i=0,1,j=0 to 2) are provided as the CAN interrupt.

23.4.1 CAN1 Wake-Up Interrupt

_______________

When a signal applied to the CAN1WU pin is on the falling edge, the CAN1WUR bit in the IIO5IR register

is set to "1" (interrupt requested). At this time, the IR bit in the CAN5IC register is set to "1" (interrupt

requested) if the CAN1WUE bit in the IIO5IE register is set to "1" (interrupt enabled).

If P77 (CAN0IN) is used as a CAN0 input port, the CAN0 wake-up interrupt is available by using event

counter mode of Timer A3 (TA3IN) that shares a pin with CAN0.

If P83 (CAN0IN/CAN1IN) is used as a CAN input port, the CAN0 and CAN1 wake-up interrupts are

________

available by using INT1 that shares a pin with CAN0IN/CAN1IN.

23.4.2 CANij Interrupts

Figure 23.41 shows a block diagram of the CANij interrupts. The followings cause the CAN-associated

interrupt request to be generated.

- The CANi slot k (k=0 to 15) completes a transmission

- The CANi slot k completes a reception

- The CANi module detects a bus error

- The CANi module moves into an error-passive state

- The CANi module moves into a bus-off state

The INTSEL bit in the CiCTLR1 register determines how an interrupt request is generated. When the

INTSEL bit is set to "0", one of the above CANi interrupt request source causes the CANij interrupts to

be generated by the OR circuit. When the INTSEL bit is set to "1", CANi transmission completed, CANi

reception completed and CANi errors (CANi bus error detection, CANi module into error-passive state

and CANi module into bus-off state) cause the CANij interrupt corresponding to each source to be

generated.

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