전자부품 데이터시트 검색엔진
  Korean  ▼
ALLDATASHEET.CO.KR

X  

Preview PDF HTML

M32C/86 데이터시트(PDF) 384 Page - Renesas Technology Corp

부품명 M32C/86
상세설명  RENESAS 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES
PDF  505 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
제조업체  RENESAS [Renesas Technology Corp]
홈페이지  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

M32C/86 데이터시트(HTML) 384 Page - Renesas Technology Corp

Back Button M32C/86 Datasheet HTML 380Page - Renesas Technology Corp M32C/86 Datasheet HTML 381Page - Renesas Technology Corp M32C/86 Datasheet HTML 382Page - Renesas Technology Corp M32C/86 Datasheet HTML 383Page - Renesas Technology Corp M32C/86 Datasheet HTML 384Page - Renesas Technology Corp M32C/86 Datasheet HTML 385Page - Renesas Technology Corp M32C/86 Datasheet HTML 386Page - Renesas Technology Corp M32C/86 Datasheet HTML 387Page - Renesas Technology Corp M32C/86 Datasheet HTML 388Page - Renesas Technology Corp Next Button
Zoom Inzoom in Zoom Outzoom out
 384 / 505 page
background image
Page 361
9
7
4
f
o
5
0
0
2
,
8
0
.
p
e
S
0
0
.
1
.
v
e
R
0
0
1
0
-
4
0
2
0
B
9
0
J
E
R
23. CAN Module
)
T
6
8
/
C
2
3
M
,
6
8
/
C
2
3
M
(
p
u
o
r
G
6
8
/
C
2
3
M
NEWDATA bit
RECREQ bit
MBOX3 to
MBOX0 bits
Start
receiving
Intermission field
CAN bus
Receive frame
INVALDATA bit
RECSUCC bit
RECSTATE bit
SISj bit
(1)
(4)
(3)
Set to "1" by program
Bus idle
Bus idle
Receive frame
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
j=0 to 15
Reception-completed
message slot number
Reception
completed
(2)
Figure 23.38 Example of CAN Data Frame Transmit Operation
23.3.3 CAN Receive Timing
Figure 23.39 shows an operation example of when the CAN receives a frame.
(1) When the RECREQ bit in the CiMCTLj register (i=0,1, j= 0 to 15) is set to "1" (receive requested),
the CAN is ready to receive the frame at anytime.
(2) When the CAN starts receiving the frame, the RECSTATE bit in the CiSTR register is set to "1"
(during reception).
(3) After the CAN frame reception is completed, the INVALDATA bit in the CiMCTLj register is set to
"1" (storing received data), the NEWDATA bit in the CiMCTLj register is set to "1" (receive com-
plete) and the RECSUCC bit in the CiSTR register is set to "1" (reception completed).
(4) After data is written to the message slot, the INVALDATA bit is set to "0" (storing receiving data)
and the SISj bit in the CiSISTR register is set to "1" (interrupt requested). The MBOX3 to MBOX0
bits in the CiSTR register store received message slot numbers.
SENTDATA bit
TRMREQ bit
MBOX3 to
MBOX0 bits
Bus idle
Start transmtting
(1)
Intermission field
CAN bus
Transmit frame
"1"
"0"
"1"
"0"
TRMACTIVE bit
"1"
"0"
Set to "1" by program
TRMSUCC bit
"1"
"0"
TRMSTATE bit "1"
"0"
SISj bit
"1"
"0"
Transmit frame
Bus idle
j=0 to 15
Transmission-completed
message slot number
Transmission completed
(2)
Figure 23.39 Example of CAN Data Frame Receive Operation



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


데이터시트 다운로드

Go To PDF Page


링크 URL



ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ] 

Alldatasheet는?   |   광고문의   |   운영자에게 연락하기   |   개인정보취급방침   |   링크 투 데이터시트    |   링크교환   |   제조사별 검색
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com