M32CSLASH86 datasheet(184/505 Pages) RENESAS

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Page 161

15. Timer (Timer A)

)

(

Timer Ai Mode Register (i=0 to 4) (Pulse Width Modulator Mode)

Symbol

Address

After Reset

TA0MR to TA4MR

035616, 035716, 035816, 035916, 035A16

0016

TMOD0

TMOD1

Operating Mode

Select Bit

Trigger Select Bit

MR1

MR3

MR2

TCK0

TCK1

Count Source

Select Bit

External Trigger Select

Bit(1)

16/8-Bit PWM Mode

Select Bit

0 : Falling edge of input signal to TAiIN pin

1 : Rising edge of input signal to TAiIN pin

0 : The TAiS bit is enabled

1 : Selected by the TAiTGH and TAiTGL

bits

0: Functions as a 16-bit pulse width modulator

1: Functions as an 8-bit pulse width modulator

0 0 : f1

0 1 : f8

1 0 : f2n(2)

1 1 : fC32

1 1 : Pulse width modulation (PWM)

mode

b1b0

Bit Name

Function

Bit

Symbol

b7b6

NOTES:

1. MR1 bit setting is enabled only when the TAiTGH and TAiTGL bits in the TRGSR register are set to

"002" (input to the TAiIN pin). The MR1 bit can be set to either "0" or "1" when the TAiTGH and

TAiTGL bits are set to "012" (TB2 overflow and underflow), "102" (TAi overflow and underflow) or

"112" (TAi overflow and underflow).

2. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15).

(b2)

Reserved Bit

Set to "0"

Figure 15.13 TA0MR to TA4MR Registers

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