M32CSLASH86 datasheet(186/505 Pages) RENESAS

186 / 505 page

Page 163

15. Timer (Timer B)

)

(

15.2 Timer B

Figure 15.16 shows a block diagram of the timer B. Figures 15.17 to 15.19 show registers associated with

the timer B. The timer B supports the following three modes. The TMOD1 and TMOD0 bits in the TBiMR

• Timer mode : The timer counts an internal count source.

• Event counter mode : The timer counts pulses from an external source or overflow and underflow of

another timer.

• Pulse period/pulse width measurement mode : The timer measures pulse period or pulse width of an

external signal.

Table 15.8 lists TBiIN pin settings.

Figure 15.16 Timer B Block Diagram

Figure 15.17 TB0 to TB5 Registers

Select Clock Source

01: Event

Counter Mode

00: Timer Mode

01: Pulse Period/Pulse Width

Measurement Mode

Reload Register

8 low-order

bits

8 high-

order

bits

Low-order Bits of Data Bus

High-order Bits of Data Bus

f2n(1)

TBj Overflow

Signal(2,3)

TBiS

fc32

Polarity Switching

and Edge Pulse

TBiIN

Counter Reset Circuit

Counter

TBi

Address

TBj

Timer B0

035116 035016

Timer B2

Timer B1

035316 035216

Timer B0

Timer B2

035516 035416

Timer B1

Timer B3

031116 031016

Timer B5

Timer B4

031316 031216

Timer B3

Timer B5

031516 031416

Timer B4

TCK1 and

TCK0

TMOD1 and

TMOD0

TCK1

i=0 to 5

NOTES:

1. The CNT3 to CNT0 bits in the TCSPR register select no

division (n=0) or divide-by-2n (n=1 to 15).

2. Overflow signal or underflow signal.

3. j=i-1, except j=2 when i=0 j=5 when i=3

TCK1 and TCK0, TMOD1 and TMOD0 : Bits in the TBiMR Register

TBiS : Bits in the TABSR and the TBSR Register

Timer Bi Register(1) (i=0 to 5)

Symbol

Address

After Reset

TB0 to TB2

035116 - 035016, 035316 - 035216, 035516 - 035416

Indeterminate

TB3 to TB5

031116 - 031016, 031316 - 031216, 031516 - 031416

Indeterminate

Timer Mode

000016 to FFFF16

Event Counter

Mode

Pulse Period/Pulse

Width Measurement

Mode

Function

Setting Range

Mode

If setting value is n, a count source

is divided by n+1

If setting value is n, a count source

is divided by n+1(2)

A count source is incremented

between one valid edge and

another valid edge of TBiIN pulse

b15

b8 b7

NOTES:

1. Use 16-bit data for reading and writing.

2. The TBi register counts how many pulse inputs are provided externally or how many times another

timer counter overflows and underflows.

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