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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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M32C/86 데이터시트(PDF) 225 Page - Renesas Technology Corp |
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M32C/86 데이터시트(HTML) 225 Page - Renesas Technology Corp |
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225 / 505 page  Page 202 9 7 4 f o 5 0 0 2 , 8 0 . p e S 0 0 . 1 . v e R 0 0 1 0 - 4 0 2 0 B 9 0 J E R 17. Serial I/O (UART) ) T 6 8 / C 2 3 M , 6 8 / C 2 3 M ( p u o r G 6 8 / C 2 3 M Stop bit Stop bit Start bit D0 D1 D2 D3 D4 D5 D6 D7 ST P D0 D1 D2 D3 D4 D5 D6 D7 ST P D0 D1 ST SP D0 D1 D2 D3 D4 D5 D6 D7 ST D8 D0 D1 D2 D3 D4 D5 D6 D7 ST D8 D0 D1 ST SP SP SP TE bit in UiC1 register TI bit in UiC1 register TXEPT bit in UiC0 register Start bit Parity bit TxDi CTSi "1" "0" "1" "L" "H" IR bit in SiTIC register Set to "0" by an interrupt request acknowledgement or by program TE bit in UiC1 register TI bit in UiC1 register TxDi TXEPT bit in UiC0 register "0" "1" "0" "1" "0" "1" i=0 to 4 The above timing applies to the following settings : • The PRYE bit in the UiMR register is set to "0" (parity disabled) • The STPS bit in the UiMR register is set to "1" (2 stop bits) • The CRD bit in the UiC0 register is set to "1" (CTS function disabled) • The UilRS bit in the UiC1 register is set to "0" (no data in the transmit buffer) Transfer Clock Tc Tc = 16 (m + 1) / fj or 16 (m + 1) / fEXT fj : count source frequency set in the UiBRG register (f1, f8, f2n(1)) fEXT : count source frequency set in the UiBRG register (external clock) m : setting value of the UiBRG register NOTES: 1. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15). IR bit in SiTIC register "0" "1" Tc Transfer Clock Pulse stops because the TE bit is set to "0" Stop bit Data is transferred from the UiTB register to the UARTi transmit register The transfer clock stops momentarily, because an "H" signal is applied to the CTS pin, when the stop bit state is verified. The transfer clock resumes running as soon as an "L" signal is applied to the CTS pin Data is set in the UiTB register Data is transferred from the UiTB register to the UARTi transmit register Data is set in the UiTB register "0" i=0 to 4 The above timing applies to the following settings : • The PRYE bit in the UiMR register is set to "1" (parity enabled) • The STPS bit in the UiMR register is set to "0" (1 stop bit) • The CRD bit in the UiC0 register is set to "0" and the CRS bit is set to "0" (CTS function selected) • The UilRS bit in the UiC1 register is set to "1" (transmission completed) Tc = 16 (m + 1) / fj or 16 (m + 1) / fEXT fj : count source frequency set in the UiBRG register (f1, f8, f2n(1)) fEXT : count source frequency set in the UiBRG register (external clock) m : setting value of the UiBRG register NOTES: 1. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15). (1) 8-bit Data Transmit Timing (with a parity and 1 stop bit) (2) 9-bit Data Transmit Timing (with no parity and 2 stop bits) "1" "0" "1" "0" Set to "0" by an interrupt request acknowledgement or by program SP SP Figure 17.14 Transmit Operation |
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