M32CSLASH86 datasheet(328/505 Pages) RENESAS

328 / 505 page

Page 305

22. Intelligent I/O (Communication Function)

)

(

Table 22.24 Pin Settings (Continued)

Port

Function

Setting

Name

PS5 Register PD11 Register IPS Register

P110

ISTxD1 output

PS5_0 = 1

G1POCR0

P112

ISRxD1 input

PS5_2 = 0

PD11_2 = 0

IPS1 = 1

NOTES:

1. Set the MOD2 to MOD0 bits in the corresponding register to "1112" (output from the communication

function used).

Figure 22.31 Transmit Operation

Figure 22.32 Receive Operation

"H"

"L"

"1"

"0"

"1"

"0"

"1"

"0"

D0 D1 D2 D3 D4 D5 D6 D7

Set data in G1TB register

SIO1TR bit

TI bit

ISTxD1 pin

Internal

Transfer clock

TXEPT bit

The above applies to the following conditions:

• The STPS bit in the G1MR register is set to "0" (1 stop bit)

• The PRYE bit in the G1MR register is set to "0" (parity disabled)

• The UFORM bit in the G1MR register is set to "0" (LSB first)

• The INV bits in the G1POCR0 to G1POCR7 registers are set to "0" (no inverse)

• The IRS bit in the G1MR register is set to "0" (no data in the G1TB register)

TI, TXEPT bit : Bits in the G1CR register

SIO1TR bit

: Bit in the IIO3IR register

Write "0" by program

if setting to "0"

D0 D1 D2 D3 D4 D5 D6 D7

Read the G1RB register

ISRxD1 pin

Internal

Transfer clock

SIO1RR bit

RI bit

The above applies to the following conditions:

• The STPS bit in the G1MR register is set to "0" (1 stop bit)

• The PRYE bit in the G1MR register is set to "0" (parity disabled)

• The UFORM bit in the G1MR register is set to "0" (LSB first)

• The INV bits in the G1POCR0 to G1POCR7 registers are set to "0" (no inverse)

SIO1RR bit : Bit in the IIO2IR register

RI bit

: Bit in the G1CR register

"H"

"L"

"1"

"0"

"1"

"0"

Write "0" by program

if setting to "0"

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