SH7014 datasheet(135/754 Pages) RENESAS

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8. Bus State Controller (BSC)

Rev.5.00 Sep. 27, 2007 Page 101 of 716

REJ09B0398-0500

Section 8 Bus State Controller (BSC)

8.1

Overview

The bus state controller (BSC) divides up the address spaces and outputs control for various types

of memory. This enables memories like DRAM, SRAM, and ROM to be linked directly to the LSI

without external circuitry.

8.1.1

Features

The BSC has the following features:

• Address space is divided into five spaces

⎯ A maximum linear 2 Mbytes for CS0 address space in modes with on-chip ROM enabled,

and a maximum linear 4 Mbytes in modes with on-chip ROM disabled

⎯ A maximum linear 4 Mbytes for each of address spaces CS1, CS2, and CS3

⎯ A maximum linear 16 Mbytes for DRAM dedicated space

⎯ Bus width can be selected for each space (8 or 16 bits)

⎯ Wait states can be inserted by software for each space

⎯ Wait states can be inserted via the WAIT pin in external memory space accesses

⎯ Outputs control signals for each space according to the type of memory connected

• On-chip ROM/RAM interfaces

⎯ On-chip RAM access of 32 bits in 1 state

⎯ On-chip ROM access of 32 bits in 1 state

• Direct interface to DRAM

⎯ Multiplexes row/column addresses according to DRAM capacity

⎯ Supports high-speed page mode and RAS down mode

• Access control for each type of memory, peripheral LSI

⎯ Address/data multiplex function

• Refresh

⎯ Supports CAS-before-RAS refresh (auto-refresh) and self-refresh

• Refresh counter can be used as an interval timer

⎯ Interrupt request generated upon compare match (CMI interrupt request signal)

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