SH7014 datasheet(137/754 Pages) RENESAS

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8. Bus State Controller (BSC)

Rev.5.00 Sep. 27, 2007 Page 103 of 716

REJ09B0398-0500

8.1.3

Pin Configuration

Table 8.1 shows the bus state controller pin configuration.

Table 8.1

Pin Configuration

Signal

I/O

Description

A21 to A0

Address output (A21 to A18 become input ports in power-on reset)

D15 to D0

I/O

16-bit data bus. D15-D0 are address output and data I/O during

address/data multiplex I/O.

CS0 to CS3

Chip select

Strobe that indicates the read cycle for ordinary space/multiplex I/O. Also

output during DRAM access.

WRH

Strobe that indicates a write cycle to the higher byte (D15 to D8) for

ordinary space/multiplex I/O. Also output during DRAM access.

WRL

Strobe that indicates a write cycle to the lower byte (D7 to D0) for ordinary

space/multiplex I/O. Also output during DRAM access.

RDWR

Strobe indicating a write cycle to DRAM (used for DRAM space)

RAS

RAS signal for DRAM (used for DRAM space)

CASH

CAS signal when accessing the higher byte (D15 to D8) of DRAM (used

for DRAM space)

CASL

CAS signal when accessing the lower byte (D7 to D0) of DRAM (used for

DRAM space)

Signal to hold the address during address/data multiplex

WAIT

Wait state request signal

8.1.4

The BSC has eight registers. These registers are used to control wait states, bus width, and

interfaces with memories like DRAM, SRAM, and ROM, as well as refresh control. The register

configurations are listed in table 8.2.

All registers are 16 bits. Do not access DRAM space before completing the memory interface

settings. All BSC registers are all initialized by a power-on reset. Values are maintained in standby

mode.

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