SH7014 datasheet(161/754 Pages) RENESAS

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8. Bus State Controller (BSC)

Rev.5.00 Sep. 27, 2007 Page 127 of 716

REJ09B0398-0500

8.4

DRAM Access

8.4.1

DRAM Direct Connection

When address space A31 to A24 = H'01 has been accessed, the corresponding space becomes a

16-Mbyte DRAM space, and the DRAM interface function can be used to directly connect this

LSI to DRAM.

Row address and column address are always multiplexed for DRAM space. The amount of row

address multiplexing can be selected as from 9 to 12 bits by setting the AMX1 and AMX0 bits of

the DCR.

Table 8.4

AMX Bits and Address Multiplex Output

Row Address

Column Address

AMX1

AMX0

Shift

Amount

Output

Address

Output

Pins

Output

Address

Output

Pins

9 bits

A21 to A15

A21 to A0

A14 to A0

A23 to A9

10 bits

A21 to A14

A21 to A0

A13 to A0

A23 to A10

11 bits

A21 to A13

A21 to A0

A12 to A0

A23 to A11

12 bits

A21 to A12

A21 to A0

A11 to A0

A23 to A12

In addition to ordinary read and write accesses, burst mode access using high speed page mode is

supported.

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