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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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SH7014 데이터시트(PDF) 162 Page - Renesas Technology Corp |
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SH7014 데이터시트(HTML) 162 Page - Renesas Technology Corp |
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162 / 754 page  8. Bus State Controller (BSC) Rev.5.00 Sep. 27, 2007 Page 128 of 716 REJ09B0398-0500 8.4.2 Basic Timing This LSI supports 2 CAS format DRAM access. The DRAM access basic timing is a minimum of 3 cycles for normal mode. Figure 8.7 shows the basic DRAM access timing. DRAM space access is controlled by RAS, CASx and RDWR signals. The following signals are associated with transfer of these actual byte locations: CASH (bits 15 to 8) and CASL (bits 7 to 0). However, the signals for ordinary space, WRx and RD, are also output during the DMAC single transfer column address cycle period. T p is the precharge cycle, Tr is the RAS assert cycle, Tc is the CAS assert cycle and T c2 is the read data fetch cycle. Tp Tr Tc1 Tc2 CK Write Read Address Data RAS CASx RDWR Data RDWR CASx RAS Row Column Figure 8.7 DRAM Bus Cycle (Normal Mode, TPC = 0, RCD = 0, No Waits) |
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