R8CSLASH15 datasheet(74/277 Pages) RENESAS

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R8C/14 Group, R8C/15 Group

11. Interrupt

Rev.2.10

Jan 19, 2006

Page 62 of 253

REJ09B0164-0210

Figure 11.4

INT0IC Register

INT0 Interrupt Control Register

(2)

Symbol

Address

After Reset

INT01C

005Dh

XX00X000b

Bit Symbol

Bit Name

Function

NOTES :

—

(b7-b6)

—

Nothing is assigned. When w rite, set to “0”.

When read, its content is indeterminate.

Only “0” can be w ritten to the IR bit. (Do not w rite “1”.)

—

(b5)

Reserved Bit

Set to “0”

POL

Polarity Sw itch Bit(4)

0 : Selects falling edge

1 : Selects rising edge(3)

Interrupt Request Bit

0 : Requests no interrupt

1 : Requests interrupt

RW(1)

ILVL0

Interrupt Priority Level Select Bit

b2 b1 b0

0 0 0 : Level 0 (interrupt disable)

0 0 1 : Level 1

0 1 0 : Level 2

0 1 1 : Level 3

1 0 0 : Level 4

1 0 1 : Level 5

1 1 0 : Level 6

1 1 1 : Level 7

ILVL1

ILVL2

To rew rite the interrupt control register, rew rite it w hen the interrupt request w hich is applicable for its register is not

generated. Refer to 20.2.6 Changing Interrupt Control Registers.

If the INTOPL bit in the INTEN register is set to “1” (both edges), set the POL bit to “0” (selects falling edge).

The IR bit may be set to “1” (requests interrupt) w hen the POL bit is rew ritten. Refer to 20.2.5 Changing Interrupt

Factor.

b7 b6 b5 b4 b3 b2 b1

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