R8CSLASH15 datasheet(32/277 Pages) RENESAS

32 / 277 page

R8C/14 Group, R8C/15 Group

5. Reset

Rev.2.10

Jan 19, 2006

Page 20 of 253

REJ09B0164-0210

Table 5.2 shows the Pin Status after Reset, Figure 5.2 shows CPU Register Status after Reset and

Figure 5.3 shows Reset Sequence.

Figure 5.2

CPU Register Status after Reset

Figure 5.3

Reset Sequence

Table 5.2

Pin Status after Reset

Pin Name

Pin Status

Input Port

P3_3 to P3_5, P3_7

Input Port

P4_5 to P4_7

Input Port

b19

Interrupt Table register(INTB)

Program Counter(PC)

User Stack Pointer(USP)

Interrupt Stack Pointer(ISP)

Static Base Register(SB)

Content of addresses 0FFFEh to 0FFFCh

Flag Register(FLG)

IPL

b15

0000h

Data Register(R0)

Data Register(R1)

Data Register(R2)

Data Register(R3)

Address Register(A0)

Address Register(A1)

Frame Base Register(FB)

00000h

0000h

CPU Clock

× 28 Cycles

0FFFCh

0FFFEh

0FFFDh

Content of Reset Vector

20 cycles or above are needed(1)

fRING-S

Internal Reset

Signal

CPU Clock

Address

(Internal Address

Signal)

NOTES:

1. This shows hardware reset

Flash memory activated time

(CPU Clock

× 72 Cycles)

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