R8CSLASH15 datasheet(141/277 Pages) RENESAS

141 / 277 page

R8C/14 Group, R8C/15 Group

14. Serial Interface

Rev.2.10

Jan 19, 2006

Page 129 of 253

REJ09B0164-0210

Figure 14.5

U0C1 and UCON Registers

UART0 Transmit / Receive Control Register 1

Symbol

Address

After Reset

U0C1

00A5h

02h

Bit Symbol

Bit Name

Function

NOTES :

Receive Complete Flag(1)

The RI bit is set to “0” w hen the higher byte of the U0RB register is read out.

0 : Data in U0TB register

1 : No data in U0TB register

—

(b7-b4)

—

Receive Enable Bit

b7 b6 b5 b4

Nothing is assigned. When w rite, set to “0”.

When read, its content is “0”.

Transmit Enable Bit

0 : Disables transmit

1 : Enables transmit

Transmit Buffer Empty Flag

0 : Disables receive

1 : Enables receive

0 : No data in U0RB register

1 : Data in U0RB register

b3 b2 b1

UART Transmit / Receive Control Register 2

Symbol

Address

After Reset

UCON

00B0h

00h

Bit Symbol

Bit Name

Function

0 : P1_5/RXD0

P1_7/CNTR00/INT10

_______

1 : P1_5/RXD0/CNTR01/INT11

______

P1_7

NOTES :

1. The CNTRSEL bit selects the input pin of CNTR0 (INTI

_____

) signal.

When the CNTR0 signal is output, it is output from the CNTR00 pin despite the CNTRSEL bit setting.

Reserved Bit

Set to “0”

CNTR0 Signal Pin Select Bit(1)

CNTRSEL

b7 b6 b5 b4

U0IRS

UART0 Transmit Interrupt

Cause Select Bit

0 : Transmit buffer empty (TI=1)

1 : Transmit completed (TXEPT=1)

—

(b1)

UART0 Continuous Receive

Mode Enable Bit

0 : Disables continuous receive mode

1 : Enables continuous receive mode

Reserved Bit

Set to “0”

b3 b2

—

(b6-b3)

b1 b0

U0RRM

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