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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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R8C/15 데이터시트(PDF) 176 Page - Renesas Technology Corp |
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R8C/15 데이터시트(HTML) 176 Page - Renesas Technology Corp |
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176 / 277 page  R8C/14 Group, R8C/15 Group 15. Clock Synchronous Serial I/O with Chip Select (SSU) Rev.2.10 Jan 19, 2006 Page 164 of 253 REJ09B0164-0210 Figure 15.18 Example of Operation in Data Transmit (4-Wire Bus Communication Mode) TDRE Bit in SSSR Register “0” “1” TEND Bit in SSSR Register “0” “1” Data write to SSTDR register Process by Program SSCK b0 SSO • When CPHS bit=0 (data change at even edges), CPOS bit=0 (“H” when clock stops) b7 SCS (Output) SSCK • When CPHS bit=1 (data change at even edges), CPOS bit=0 (“H” when clock stops) CPHS, CPOS : Bits in SSMR register 1 Frame TDRE Bit in SSSR Register “0” “1” TEND Bit in SSSR Register “0” “1” Data write to SSTDR register Process by Program 1 Frame High-Impedance b0 b7 High-Impedance SCS (Output) TXI interrupt request is generated b7 b0 SSO 1 Frame 1 Frame b6 b6 TXI interrupt request is generated TEI interrupt request is generated b6 b7 b0 b6 TEI interrupt request is generated TXI interrupt request is generated TXI interrupt request is generated |
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