R8CSLASH15 datasheet(222/277 Pages) RENESAS

222 / 277 page

R8C/14 Group, R8C/15 Group

18. Flash Memory Version

Rev.2.10

Jan 19, 2006

Page 210 of 253

REJ09B0164-0210

18.4.5

Full Status Check

When an error occurs, the FMR06 to FMR07 bits in the FMR0 register are set to “1”, indicating

occurrence of each specific error. Therefore, Checking these status bits (full status check) can

determine the executed result.

Table 18.6 lists the Errors and FMR0 Register Status. Figure 18.14 shows the Full Status Check and

Handling Procedure for Each Error.

NOTES:

1. The microcomputer enters read array mode by writing “FFh” in the second bus cycle of these

commands, at the same time the command code written in the first bus cycle will disabled.

Table 18.6

Errors and FMR0 Register Status

FRM00 Register (Status

Error

Error occurrence condition

FMR07(SR5) FMR06(SR4)

Command

Sequence

Error

• When any command is not written correctly

• When invalid data other than those that can be written

in the second bus cycle of the block erase command is

written (i.e., other than “D0h” or “FFh”)(1)

• When executing the program command or block erase

command while rewriting is disabled using the FMR02

bit in the FMR0 register, the FMR15 or FMR16 bit in the

FMR1 register.

• When inputting and erasing the address in which the

Flash memory is not allocated during the erase

command input

• When executing to erase the block which disables

rewriting during the erase command input.

• When inputting and writing the address in which the

Flash memory is not allocated during the write

command input.

• When executing to write the block which disables

rewriting during the write command input.

Erase Error

• When the block erase command is executed but not

automatically erased correctly

Program Error

• When the program command is executed but not

automatically programmed correctly.

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