4513 datasheet(56/210 Pages) RENESAS

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4513/4514 Group User’s Manual

HARDWARE

1-43

FUNCTION BLOCK OPERATIONS

Table 16 Change of successive comparison register AD during A-D conversion

Comparison voltage (Vref) value

Change of successive comparison register AD

At starting conversion

(7) Operation description

A-D conversion is started with the A-D conversion start instruction

(ADST). The internal operation during A-D conversion is as follows:

When A-D conversion starts, the register AD is cleared to

“00016.”

Next, the topmost bit of the register AD is set to “1,” and the

comparison voltage Vref is compared with the analog input volt-

age VIN.

When the comparison result is Vref < VIN, the topmost bit of the

Vref > VIN, it is cleared to “0.”

The 4513/4514 Group repeats this operation to the lowermost bit of

the register AD to convert an analog value to a digital value. A-D

conversion stops after 62 machine cycles (46.5

µs when f(XIN) =

4.0 MHz in high-speed mode) from the start, and the conversion re-

sult is stored in the register AD. An A-D interrupt activated condition

is satisfied and the ADF flag is set to “1” as soon as A-D conversion

completes (Figure 27).

U1: 1st comparison result

U3: 3rd comparison result

U9: 9th comparison result

U2: 2nd comparison result

U8: 8th comparison result

UA: 10th comparison result

1st comparison

2nd comparison

3rd comparison

After 10th comparison

completes

-----

A-D conversion result

VDD

1024

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