| 전자부품 데이터시트 검색엔진 |
|
HD64F2144B 데이터시트(PDF) 73 Page - Renesas Technology Corp |
|
|
|||||||||||||||||||||||||||||
HD64F2144B 데이터시트(HTML) 73 Page - Renesas Technology Corp |
|
73 / 546 page ![]() Section 2 CPU Rev. 1.00 Jun.24, 2005 Page 41 of 510 REJ09B0241-0100 Table 2.6 Shift Instructions Instruction Size* Function SHAL SHAR B/W/L Rd (shift) → Rd Performs an arithmetic shift on data in a general register. 1-bit or 2 bit shift is possible. SHLL SHLR B/W/L Rd (shift) → Rd Performs a logical shift on data in a general register. 1-bit or 2 bit shift is possible. ROTL ROTR B/W/L Rd (rotate) → Rd Rotates data in a general register. 1-bit or 2 bit rotation is possible. ROTXL ROTXR B/W/L Rd (rotate) → Rd Rotates data including the carry flag in a general register. 1-bit or 2 bit rotation is possible. Note: * Size refers to the operand size. B: Byte W: Word L: Longword |
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |