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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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HD64F2144B 데이터시트(PDF) 96 Page - Renesas Technology Corp |
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HD64F2144B 데이터시트(HTML) 96 Page - Renesas Technology Corp |
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96 / 546 page  Section 3 MCU Operating Modes Rev. 1.00 Jun.24, 2005 Page 64 of 510 REJ09B0241-0100 Bit Bit Name Initial Value R/W Description 3 FLSHE 0 R/W Flash Memory Control Register Enable Enables or disables CPU access for flash memory registers (FLMCR1, FLMCR2, EBR1, EBR2), control registers in power-down state (SBYCR, LPWRCR, MSTPCRH, MSTPCRL), and control registers of on- chip peripheral modules (PCSR, SYSCR2). 0: Registers in power-down state and control registers of on-chip peripheral modules are accessed in an area from H'(FF)FF80 to H'(FF)FF87. 1: Control registers of flash memory are accessed in an area from H'(FF)FF80 to H'(FF)FF87. 2 — 0 R/(W) Reserved The initial value should not be changed. 1 0 ICKS1 ICKS0 0 0 R/W R/W Internal Clock Source Select 1, 0 These bits select a clock to be input to the timer counter (TCNT) and a count condition together with bits CKS2 to CKS0 in the timer control register (TCR). For details, refer to section 10.3.4, Timer Control Register (TCR). Note: * Available only for the H8S/2144B. |
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