TDA9103 datasheet(11/27 Pages) STMICROELECTRONICS

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VREF

10k

Ω

22k

Ω

DC Control Voltage

10k

Ω

Figure 5 :

Example of Practical DC Control

Voltage Generation

Figure 6

1.6V

HSYNC

Figure 7 : Input Structure

OPERATING DESCRIPTION

GENERAL CONSIDERATIONS

Power Supply

The typical value of the power supply voltage VCC

is 12V. Perfect operation is obtained if VCC is main-

tained in the limits : 10.8V

→ 13.2V.

In order to avoid erratic operation of the circuit

during the transient phase of VCC switching on, or

switching off, the value of VCC is monitored and the

outputs of the circuit are inhibited if it is too low.

In order to have a very good power supply rejection,

the circuit is internally powered by several internal

voltage references (The unique typical value of

which is 8V). Two of these voltage references are

externally accessible, one for the vertical part and

one for the horizontal part. These voltage refer-

ences can be used for the DC control voltages

applied on the concerned pins by the way of poten-

tiometers or digital to analog converters (DAC’s).

Furthermore it is possible to filter the a.m. voltage

references by the use of external capacitor con-

nected to ground, in order to minimize the noise

and consequently the ”jitter” on vertical and hori-

zontal output signals.

DC Control Adjustments

The circuit has 10 adjustment capabilities : 3 for the

horizontal part, 1 for the SMPS part, 2 for the E/W

correction, 4 for the vertical part.

The corresponding inputs of the circuit has to be

driven with a DC voltage typically comprised be-

tween 2 and 6V for a value of the internal voltage

reference of 8V.

More precisely, the control voltages have to be

maintained between VREF/4 and 3/4

⋅ VREF. The

application of control voltages outside this range is

not dangerousfor the circuit but the good operation

is not guaranted (except for Pin 2 : duty cycle

adjusment. See outputs inhibition paragraph).

The input currents of the DC control inputs are

typically very low (about a few

µA). Depending on

the internal structure of the inputs, the input cur-

rents can be positive or negative (sink or source).

HORIZONTAL PART

Input section

The horizontal input is designed to be sensitive to

TTL signals typically comprised between 0 and 5V.

The typical threshold of this input is 1.6V. This input

stage uses an NPN differential stage and the input

current is very low.

Concerning the duty cycle of the input signal, the

following signals may be applied to the circuit.

Using internal integration, both signals are recog-

nized on condition that Z/T

≤ 25%. Synchronisation

occurs on the leading edge of the rectified signal.

The minimum value of Z is 0.7

µs.

PLL1

The PLL1 is composed of a phase comparator, an

external filter and a Voltage Controlled Oscillator

(VCO).

The phase comparatoris a ”phase frequency” type,

designed in CMOS technology. This kind of phase

detector avoids locking on false frequencies. It is

followed by a ”charge pump”, composed of 2 cur-

rent sources sink and source (I = 1mA typ.)

TDA9103

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