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TDA9103 데이터시트(PDF) 16 Page - STMicroelectronics |
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TDA9103 데이터시트(HTML) 16 Page - STMicroelectronics |
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16 / 27 page ![]() V REF H-amp Reg-in Compensation Clamp I SENSE H-FREQ Buffer SMPS OUT + - EA RAP CYC - + S R Basc 40 41 42 22 39 Figure 18 : SMPS Block Diagram H Osc Sawtooth SMPS Drive SMPS Current 1.6V 6.4V 0.75T 0.25T Error Amplifier Output (1.2V Max) Figure 19 : SMPS Timing Diagram Usys t U 0 TDA9103 Hamp Adjust V REF 4.8V S WITCHING REGULATOR Flyback P eak Dete ction a nd Re gulation Hyoke HDRIVE Usys t is a pproximatively proportiona l to Hfreq S te p-up Conve rte r H S ca n ning P art Figure 20 : H Scanning Amplitude Regulation Example The following functions are implemented in the TDA9103 : - A DC controlled variable gain amplifier allowing a variation of ±14% of the voltage reference. This is used to set the horizontal image ampli- tude. - An error amplifier, the non inverting input of which is connected to the above mentioned adjustable voltage reference. The inverting input and the output of the error amplifier are externally accessible. - A comparator which determines the conduction of the external transistor by comparing the output voltage of the error amplifier and the voltage applied on Pin 42 (ISENSE), which is the image of the current in the power transistor (current mode principle). - A flip-flop which memorizes the on or off state of the power transistor. - An output buffer stage (open collector). TDA9103 16/27 |
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