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PCM3168APAPR 데이터시트(PDF) 35 Page - Texas Instruments

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부품명 PCM3168APAPR
상세설명  24-Bit, 96-kHz/192-kHz, 6-In/8-Out Audio Codec with Differential Input/Output
PDF  66 Pages
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제조업체  TI [Texas Instruments]
홈페이지  http://www.ti.com
Logo TI - Texas Instruments

PCM3168APAPR 데이터시트(HTML) 35 Page - Texas Instruments

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TIMING REQUIREMENTS: SCL AND SDA
t
BUF
t
D-SU
t
D-HD
t
SDA-R
t
SDA-F
t
P-SU
t
SCL-F
t
S-HD
t
LOW
t
SCL-R
t
HI
t
S-SU
t
S-HD
START
Repeated
START
STOP
SDA
SCL
PCM3168A
PCM3168A-Q1
www.ti.com ......................................................................................................................................................................................... SBAS452 – SEPTEMBER 2008
Figure 55. SCL and SDA Control Interface Timing
Timing Requirements for Figure 55
PCM3168A, PCM3168A-Q1
STANDARD MODE
FAST MODE
SYMBOL
PARAMETER
MIN
MAX
MIN
MAX
UNIT
fSCL
SCL clock frequency
100
400
kHz
tBUF
Bus free time between STOP and START condition
4.7
1.3
µs
tLOW
Low period of the SCL clock
4.7
1.3
µs
tHI
High period of the SCL clock
4.0
0.6
µs
tS-SU
Setup time for START/Repeated START condition
4.7
0.6
µs
tS-HD
Hold time for START/Repeated START condition
4.0
0.6
µs
tD-SU
Data setup time
250
100
ns
tD-HD
Data hold time
0
3450
0
900
ns
tSCL-R
Rise time of SCL signal
1000
20 + 0.1 CB
300
ns
tSCL-F
Fall time of SCL signal
1000
20 + 0.1 CB
300
ns
tSDA-R
Rise time of SDA signal
1000
20 + 0.1 CB
300
ns
tSDA-F
Fall time of SDA signal
1000
20 + 0.1 CB
300
ns
tP-SU
Setup time for STOP condition
4.0
0.6
µs
tGW
Allowable glitch width
N/A
50
CB
Capacitive load for SDA and SCL line
400
100
pF
Noise margin at high level for each connected device
VNH
0.2 × VDD
0.2 × VDD
V
(including hysteresis)
Noise margin at low level for each connected device
VNL
0.1 × VDD
0.1 × VDD
V
(including hysteresis)
VHYS
Hysteresis of Schmitt-trigger input
N/A
0.05 × VDD
V
Copyright © 2008, Texas Instruments Incorporated
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Product Folder Link(s): PCM3168A PCM3168A-Q1



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