PCM3168APAPR datasheet(38/66 Pages) TI

38 / 66 page

PCM3168A

PCM3168A-Q1

SBAS452 – SEPTEMBER 2008 ......................................................................................................................................................................................... www.ti.com

DEC

HEX

MRST

SRST

—

SRDA1

SRDA0

MRST

Mode control register reset for the ADC and DAC

This bit sets the mode control register reset to the default value. Pop-noise may be generated.

Returning the MRST bit to '1' is unneccesary, because it is automatically set to '1' after the mode

control register is reset.

Default value = 1.

MRST

Mode control register reset

Set default value

Normal operation (default)

SRST

System reset for the ADC and DAC

This bit controls system reset, the relation between system clock and sampling clock

re-synchronization, and ADC operation and DAC operation restart. The mode control register is

not reset and the PCM3168A and PCM3168A-Q1 do not go into a power-down state. The fade-in

sequence is supported in the resume process, but pop-noise may be generated. Returning the

SRST bit to '1' is unneccesary; it is automatically set to '1' after triggering a system reset.

Default value = 1.

SRST

System reset

Resynchronization

Normal operation (default)

SRDA[1:0]

DAC Sampling mode select

These bits control the sampling mode of DAC operation. In Auto mode, the sampling mode is

automatically set according to multiples between the system clock and sampling clock, single rate

for 512 fS and 768 fS, dual rate for 256 fS or 384 fS, and quad rate for 128 fS and 192 fS.

Default value = 00.

SRDA

DAC Sampling mode select

Auto (default)

Single rate

Dual rate

Quad rate

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