ML5805
RF MICRO DEVICES®, RFMD®, OPTIMUM TECHNOLOGY MATCHING®, ENABLING WIRELESS CONNECTIVITY™, POWERSTAR®, POLARIS™ TOTAL RADIO™ ULTIMATEBLUE™ AND FASTWAVE™ ARE TRADEMARKS OF RFMD, LLC. BLUETOOTH IS A TRADEMARK OWNED BY
BLUETOOTH SIG, INC., U.S.A. AND LICENSED FOR USE BY RFMD. ALL OTHER TRADE NAMES, TRADEMARKS AND REGISTERED TRADEMARKS ARE THE PROPERTY OF THEIR RESPECTIVE OWNERS. ©2006, RF MICRO DEVICES, INC.
PRELIMINARY DATA SHEET
APRIL 2008
EDS-106041 REV P01
7628 THORNDIKE ROAD, GREENSBORO, NC 27409-9421 · FOR SALES OR TECHNICAL
REV A1 DS071026 SUPPORT, CONTACT RFMD AT (+1) 336-678-5570 OR SALES-SUPPORT@RFMD.COM
5
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
FDEV
Transmit Modulation Deviation
Data Rate=1.1520Mbps
Data Rate=1.5360Mbps
Data Rate=1.7554Mbps
Data Rate=2.0480Mbps
±400
±512
±596
±680
kHz
ZTXO
Output Impedance
at TXO pin
TBD
Ω
BT
Transmit Filter Bandwidth / Symbol
Rate Ratio
Data Rate=1.1520Mbps
Data Rate=1.5360Mbps
Data Rate=1.7554Mbps
Data Rate=2.0480Mbps
0.5
0.9
0.8
0.7
PSPUR
PLL reference spurious
VFREF < 2 Vp-p clip-sine
-70
dBc
PLO
TX LO feed through, LO harmonics
and sub-harmonics
2
PTXO =+21dBm, FSPUR =1/3,
2/3, 4/3, and 5/3 FTXO
-40
dBc
2
nd Harmonic
-45
dBc
PHarm
TX Harmonics, PTXO =+21dBm
3
rd Harmonic
-25
dBc
INTERFACE LOGIC LEVELS
CMOS DIGITAL INPUT PINS (XCEN, RXON, DIN, DATASEL)
VIH
Input high voltage
VDD*0.7
VDD
V
VIL
Input low voltage
0
VDD*0.3
V
IB
Input bias current
All states
-5
5
μA
CIN
Input capacitance
1MHz test frequency
4
pF
CMOS DIGITAL OUTPUT PINS (SW_CTRL, RXCLK, DOUT)
VOH
SW_CTRL output high voltage
Sourcing 5.0mA
VDD-0.4
V
VOL
SW_CTRL output low voltage
Sinking 5.0mA
0.4
V
Io
SW_CTRL source/sink current
±5.0
±8.0
mA
VOH
RXCLK (recovered clock) output
high voltage
Sourcing 0.1mA
VDD–0.4
V
VOL
RXCLK (recovered clock) output low
voltage
Sinking 0.1mA
0.4
V
VOH
DOUT (data output) output high
voltage
Sourcing 0.1mA
VDD–0.4
V
VOL
DOUT (data output) output low
voltage
Sinking 0.1mA
0.4
V
ANALOG OUTPUT PINS (AOUT)
VODC
Quiescent output voltage @ AOUT
1.15
V
VOPK
Output voltage swing @ AOUT
0.8
VP-P
3 WIRE SERIAL BUS TIMING
tr
CLK input rise time (note 1)
15
ns
tf
CLK input fall time (note 1)
15
ns
tck
CLK period
50
ns
tew
EN pulse width
200
ns
tl
Delay from last clock rising edge to
rise of EN
15
ns
2 TX frequency = F
TXO, TX power = PTXO
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