Altera Corporation

763

Classic EPLD Family Data Sheet

Notes to tables:

(1)

These values are specified in Table 3 on page 758.

(2)

See Application Note 78 (Understanding MAX 5000 & Classic Timing) in this data book for information on internal

timing parameters.

(3)

The non-Turbo adder must be added to this parameter when the Turbo Bit option is off.

(4)

Sample-tested only for an output change of 500 mV.

(5)

(6)

Measured with a device programmed as a 16-bit counter.

(7)

Sample-tested only. This parameter is a guideline based on extensive device characterization. This parameter

applies for both global and array clocking.

Table 11. EP610-25, EP610-30 & EP610-35 Internal Timing Parameters

Symbol

Parameter

Condition

EP610-25

EP610-30

EP610-35

Unit

Min

Max

Min

Max

Min

Max

Input pad and buffer delay

8.0

9.0

11.0

ns

I/O input pad and buffer delay

2.0

2.0

2.0

ns

Logic array delay

11.0

14.0

15.0

ns

Output buffer and pad delay

C1 = 35 pF

6.0

7.0

9.0

ns

Output buffer enable delay

C1 = 35 pF

6.0

7.0

9.0

ns

Output buffer disable delay

C1 = 5 pF

6.0

7.0

9.0

ns

Register setup time

11.0

11.0

12.0

ns

Register hold time

10.0

10.0

10.0

ns

Array clock delay

13.0

16.0

17.0

ns

Global clock delay

1.0

1.0

0.0

ns

Feedback delay

3.0

5.0

8.0

ns

Register clear time

13.0

16.0

17.0

ns