Altera Corporation

773

Classic EPLD Family Data Sheet

Notes to tables:

(1)

These values are specified in Table 15 on page 770.

(2)

See Application Note 78 (Understanding MAX 5000 & Classic Timing) in this data book for more information on Classic

timing parameters.

(3)

The non-Turbo adder must be added to this parameter when the Turbo Bit option is off.

(4)

Sample-tested only for an output change of 500 mV.

(5)

(6)

Measured with a device programmed as a 24-bit counter.

(7)

Sample-tested only. This parameter is a guideline based on extensive device characterization and applies for both

global and array clocking.

Table 20. EP910 Internal Timing Parameters

Symbol

Parameter

Condition

EP910-30

EP910-35

EP910-40

Unit

Min

Max

Min

Max

Min

Max

Input pad and buffer delay

9.0

10.0

13.0

ns

I/O input pad and buffer delay

3.0

3.0

3.0

ns

Logic array delay

14.0

16.0

17.0

ns

Output buffer and pad delay

C1 = 35 pF

7.0

9.0

10.0

ns

Output buffer enable delay

C1 = 35 pF

7.0

9.0

10.0

ns

Output buffer disable delay

C1 = 5 pF

7.0

9.0

10.0

ns

Register setup time

12.0

13.0

15.0

ns

Register hold time

12.0

12.0

12.0

ns

Array clock delay

17.0

19.0

20.0

ns

Global clock delay

2.0

2.0

1.0

ns

Feedback delay

4.0

6.0

8.0

ns

Register clear time

17.0

19.0

20.0

ns