9202 datasheet(83/175 Pages) STMICROELECTRONICS

83 / 175 page

83/175

UPSD3254A, UPSD3254BV, UPSD3253B, UPSD3253BV

Special Function Register for the DDC Interface

There are eight SFR in the DDC interface:

RAMBUF, DDCCON, DDCADR, DDCDAT are

DDC registers.

S1CON, S1STA, S1DAT, S1ADR are I2C Inter-

face registers, same as the ones described in the

standalone I2C bus.

DDCDAT Register. DDC1

DATA

for

transmission (DDCDAT: 0D5H)

8-bit READ and WRITE register.

Indicates DATA BYTE to be transmitted in

DDC1 protocol.

DDCADR Register. Address pointer for DDC in-

terface (DDCADR: 0D6H)

8-bit READ and WRITE register.

Address pointer with the capability of the post

increment. After each access to RAMBUF

DDC1 interface), the content of this register will

be increased by one. It’s available both in

DDC1, DDC2 (DDC2B, DDC2B+, and

DDC2AB) and system operation.

Table 60. DDC SFR Memory Map

SFR

Addr

Reg

Name

Bit Register Name

Reset

Value

Comments

D4 RAMBUF

DDC Ram

Buffer

DDCDAT

DDC Data

xmit register

D6 DDCADR

Addr pointer

D7 DDCCON

—

EX_DAT SWENB DDC_AX DDCINT DDC1EN SWHINT

DDC Control

9202 데이터시트(PDF) 83 Page - STMicroelectronics

9202 데이터시트(HTML) 83 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL