9202 datasheet(85/175 Pages) STMICROELECTRONICS

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UPSD3254A, UPSD3254BV, UPSD3253B, UPSD3253BV

Table 62. SWNEB Bit Function

SWENB

DDC1 or DDC2b Mode Disabled

DDC1 or DDC2b Mode Enabled

DDCCON.bit2 = 0 (DDC1 Mode Disable) or

S1CON.bit6 = 0 (I2C Mode Disable)

DDCCON.bit2 = 1 (DDC1 Mode Enable) or

S1CON.bit6 = 1 (I2C Mode Enable)

In this state, the DDC unit is disabled. The DDC

SRAM cannot be accessed by the MCU. No MCU

interrupt and no DDC activity will occur.

MCU cannot access internal DDC SRAM: DDC

SRAM address space is re-assigned to external

data space.

In this state, the DDC is enabled and the unit is in

automatic mode. The DDC SRAM cannot be

accessed by the MCU – only the DDC unit has

access.

MCU cannot access internal DDC SRAM: data

space FF00h-FFFFh is dedicated to DDC SRAM.

In this state, the DDC unit is disabled, BUT with

SWENB=1, the MCU can access the SRAM. This

state is used to load the DDC SRAM with the

correct data for automatic modes. No MCU

interrupt and no DDC activity will occur.

MCU can access DDC SRAM: data space FF00h-

FFFFh is dedicated to DDC SRAM.

In this state, the DDC SRAM can be accessed by

the MCU. The DDC unit does not use the DDC

SRAM when SWENB=1. Since the DDC unit is in

manual mode, the DDC unit generates an MCU

interrupt for each byte transferred. The byte

transferred is held in the I2C S1DAT SFR register.

MCU can access DDC SRAM.

9202 데이터시트(PDF) 85 Page - STMicroelectronics