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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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9202 데이터시트(PDF) 140 Page - STMicroelectronics |
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9202 데이터시트(HTML) 140 Page - STMicroelectronics |
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140 / 175 page  UPSD3254A, UPSD3254BV, UPSD3253B, UPSD3253BV 140/175 Table 104. Status During Power-on RESET, Warm RESET and Power-down Mode Note: 1. The SR_cod and PeriphMode Bits in the VM Register are always cleared to '0' on Power-on RESET or Warm RESET. Port Configuration Power-On RESET Warm RESET Power-down Mode MCU I/O Input mode Input mode Unchanged PLD Output Valid after internal PSD configuration bits are loaded Valid Depends on inputs to PLD (addresses are blocked in PD Mode) Address Out Tri-stated Tri-stated Not defined Peripheral I/O Tri-stated Tri-stated Tri-stated Register Power-On RESET Warm RESET Power-down Mode PMMR0 and PMMR2 Cleared to '0' Unchanged Unchanged Macrocells flip-flop status Cleared to '0' by internal Power-on RESET Depends on .re and .pr equations Depends on .re and .pr equations VM Register(1) Initialized, based on the selection in PSDsoft Configuration menu Initialized, based on the selection in PSDsoft Configuration menu Unchanged All other registers Cleared to '0' Cleared to '0' Unchanged |
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