CoreMP7

v2.6

11

The Program Status Registers

The CoreMP7 core contains a CPSR and five SPSRs for exception handlers to use. The program status registers the

following:

•

Hold the condition code flags

•

Control the enabling and disabling of interrupts

•

Set the processor operating mode

The arrangement of bits is shown in Figure 7.

The Condition Code Flags

The N, Z, C, and V bits are the condition code flags. You can set these bits by arithmetic and logical operations. The

flags can also be set by MSR and LDM instructions. The CoreMP7 processor tests these flags to determine whether to

execute an instruction.

All instructions can be executed conditionally in ARM state. In Thumb state, only the Branch instruction can be

executed conditionally. For more information about conditional execution, see the ARM Architecture Reference

Manual.

Figure 7 •

Program Status Register Format

Condition

Code Flags

Reserved

Control Bits

Overflow

Zero

Negative or Less Than

Mode Bits

State Bit

FIQ Disable

IRQ Disable

31 30 29 28

NZ

CV

27 26 25 24 23

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F

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