CoreMP7

v2.6

5

The signals of the CoreMP7 are listed in Table 2.

Figure 3 •

CoreMP7 Functional Diagram

CLK

Clock

Interrupts

Bus Control

Arbitration

Debug

CLKEN

nIRQ

nFIQ

nRESET

CFGBIGEND

DMORE

LOCK

DBGINSTRVALID

DBGRQ

DBGBREAK

DBGACK

DBGnEXEC

DBGEXT[1]

DBGEXT[0]

DBGEN

DBGRNG[1]

DBGRNG[0]

DBGCOMMRX

DBGCOMMTX

DBGTCKEN

DBGTMS

DBGTDI

DBGnTRST

DBGTDO

DBGnTDOEN

ADDR[31:0]

WDATA[31:0]

RDATA[31:0]

ABORT

WRITE

SIZE[1:0]

PROT[1:0]

TRANS[1:0]

CPnTRANS

CPnOPC

CPnMREQ

CPSEQ

CPTBIT

CPnl

CPA

CPB

Synchronized

EmbeddedICE-RT

Scan Debug

Access Port

Memory

Interface

Memory

Management

Interface

Coprocessor

Interface

CoreARM7

Table 2 •

Signal Descriptions

Name

Type

Description

ABORT

Input

Memory abort or bus error

CFGBIGEND

Input

Big/Little Endian configuration

CLK

Input

Clock

CLKEN

Input

Clock enable

CPA

Input

Coprocessor absent

CPB

Input

Coprocessor busy

DBGBREAK

Input

EICE breakpoint/watchband indicator

DBGEN

Input

Debug enable

DBGEXT[1:0]

Input

EICE external input 0

Note: The CoreMP7 is available with either the native ARM7 bus interface or with an AHB wrapper. The use of the AHB wrapper changes

or transforms some of the signals in Table 2. This is discussed in detail later in this document.