LTC1709-8_1 datasheet(8/28 Pages) LINER

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LTC1709-8/LTC1709-9

PI FU CTIO S

TG2, TG1 (Pins 24, 35): High Current Gate Drives for Top

N-Channel MOSFETS. These are the outputs of floating

drivers with a voltage swing equal to INTVCC superim-

posed on the switch node voltage SW.

SW2, SW1 (Pins 25, 34): Switch Node Connections to

Inductors. Voltage swing at these pins is from a Schottky

diode (external) voltage drop below ground to VIN.

BOOST2, BOOST1 (Pins 26, 33): Bootstrapped Supplies

to the Topside Floating Drivers. External capacitors are

connected between the BOOST and SW pins, and Schottky

diodes are connected between the BOOST and INTVCC

pins.

BG2, BG1 (Pins 27, 31): High Current Gate Drives for

Bottom N-Channel MOSFETS. Voltage swing at these pins

is from ground to INTVCC.

PGND (Pin 28): Driver Power Ground. Connect to sources

of bottom N-channel MOSFETS and the (–) terminals of

CIN.

INTVCC (Pin 29): Output of the Internal 5V Linear Low

Dropout Regulator and the EXTVCC Switch. The driver and

control circuits are powered from this voltage source.

Decouple to power ground with a 1

µF ceramic capacitor

placed directly adjacent to the IC and minimum of 4.7

µF

additional tantalum or other low ESR capacitor.

EXTVCC (Pin 30): External Power Input to an Internal

Switch. This switch closes and supplies INTVCC, bypass-

ing the internal low dropout regulator whenever EXTVCC is

higher than 4.7V. See EXTVCC Connection in the Applica-

tions Information section. Do not exceed 7V on this pin

and ensure VEXTVCC ≤ VIN.

VIN (Pin 32): Main Supply Pin. Should be closely de-

coupled to the IC’s signal ground pin.

PLLIN (Pin 6): External Synchronization Input to Phase

Detector. This pin is internally terminated to SGND with

50k

Ω. The phase-locked loop will force the rising top gate

signal of controller 1 to be synchronized with the rising

edge of the PLLIN signal.

NC (Pins 7, 36): Do not connect.

ITH (Pin 8): Error Amplifier Output and Switching Regula-

tor Compensation Point. Both current comparator’s thresh-

olds increase with this control voltage. The normal voltage

range of this pin is from 0V to 2.4V

SGND (Pin 9): Signal Ground. This pin is common to both

controllers. Route separately to the PGND pin.

VDIFFOUT (Pin 10): Output of a Differential Amplifier. This

pin provides true remote output voltage sensing. VDIFFOUT

normally drives an external resistive divider that sets the

output voltage.

VOS–, VOS+ (Pins 11, 12): Inputs to an Operational Ampli-

fier. Internal precision resistors capable of being elec-

tronically switched in or out can configure it as a differential

amplifier or an uncommitted op amp.

ATTENOUT (Pin 15): Voltage Feedback Signal Resistively

Divided According to the VID Programming Code.

ATTENIN (Pin 16): The Input to the VID Controlled Resis-

tive Divider.

VID0–VID4 (Pins 17,18, 19, 20, 21): VID Control Logic

Input Pins.

VBIAS (Pin 22): Supply Pin for the VID Control Circuit.

PGOOD (Pin 23): Open-Drain Logic Output. PGOOD is

pulled to ground when the voltage on the EAIN pin is not

within

±7.5% of its set point.

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