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M68HC08 데이터시트(PDF) 49 Page - Freescale Semiconductor, Inc |
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M68HC08 데이터시트(HTML) 49 Page - Freescale Semiconductor, Inc |
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49 / 188 page ![]() Computer Operating Properly Module (COP) COP Control Register MC68HC908RF2 — Rev. 4.0 Data Sheet MOTOROLA Computer Operating Properly Module (COP) 49 4.3.6 Reset Vector Fetch A reset vector fetch occurs when the vector address appears on the data bus. A reset vector fetch clears the COP prescaler. 4.3.7 COPD The COPD signal reflects the state of the COP disable bit (COPD) in the configuration register. (See Section 3. Configuration Register (CONFIG)). 4.3.8 COPRS The COPRS signal reflects the state of the COP rate select bit (COPRS) in the configuration register. (See Section 3. Configuration Register (CONFIG)). 4.4 COP Control Register The COP control register is located at address $FFFF and overlaps the reset vector. Writing any value to $FFFF clears the COP counter and starts a new timeout period. Reading location $FFFF returns the low byte of the reset vector. 4.5 Interrupts The COP does not generate CPU interrupt requests. 4.6 Monitor Mode The COP is disabled in monitor mode when VTST is present on the IRQ pin or on the RST pin. 4.7 Low-Power Modes The WAIT and STOP instructions put the MCU in low power-consumption standby modes. 4.7.1 Wait Mode The COP remains active in wait mode. To prevent a COP reset during wait mode, periodically clear the COP counter in a CPU interrupt routine. Address: $FFFF Bit 7 654321 Bit 0 Read: LOW BYTE OF RESET VECTOR Write: CLEAR COP COUNTER Reset: Unaffected by reset Figure 4-2. COP Control Register (COPCTL) Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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