M68HC08 datasheet(74/188 Pages) FREESCALE

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Internal Clock Generator Module (ICG)

Data Sheet

MC68HC908RF2 — Rev. 4.0

Internal Clock Generator Module (ICG)

MOTOROLA

6.3.4.2 Internal Clock Activity Detector

The internal clock activity detector looks for at least one falling edge on the

low-frequency base clock (IBASE) every time the external reference (EREF) is low.

Since EREF is less than half the frequency of IBASE, this should occur every time.

If it does not occur two consecutive times, the internal clock inactivity indicator

(IOFF) is set. IOFF will be cleared the next time there is a falling edge of IBASE

while EREF is low.

The internal clock stable bit (ICGS) is set when IBASE is within approximately 5

percent of the target 307.2 kHz

±25 percent for two consecutive measurements.

ICGS is cleared when IBASE is outside the 5 percent of the target 307.2 kHz

±25

percent, the internal clock generator is disabled (ICGEN is clear), or when IOFF is

set.

6.3.4.3 External Clock Activity Detector

The external clock activity detector looks for at least one falling edge on the

external clock (ECLK) every time the internal reference (IREF) is low. Since IREF

is less than half the frequency of ECLK, this should occur every time. If it does not

occur two consecutive times, the external clock inactivity indicator (EOFF) is set.

EOFF will be cleared the next time there is a falling edge of ECLK while IREF is

low.

The external clock stable bit (ECGS) is also generated in the external clock activity

detector. ECGS is set on a falling edge of the external stabilization clock

(ESTBCLK). This will be 4096 ECLK cycles after the external clock generator on

bit (ECGON) is set. ECGS is cleared when the external clock generator is disabled

(ECGON is clear) or when EOFF is set.

6.3.5 Clock Selection Circuit

The clock selection circuit, shown in Figure 6-5, contains two clock switches which

generate the oscillator output clock (CGMXCLK) from either the internal clock

(ICLK) or the external clock (ECLK). The clock selection circuit also contains a

divide-by-two circuit which creates the clock generator output clock (CGMOUT),

which generates the bus clocks.

6.3.5.1 Clock Selection Switch

The clock select switch creates the oscillator output clock (CGMXCLK) from either

the internal clock (ICLK) or the external clock (ECLK), based on the clock select bit

(CS; set selects ECLK, clear selects ICLK). When switching the CS bit, both ICLK

and ECLK must be on (ICGON and ECGON set). The clock being switched to must

also be stable (ICGS or ECGS set).

Freescale Semiconductor, Inc.

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Go to: www.freescale.com

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