PCI1221 datasheet(51/123 Pages) TI

51 / 123 page

PCI1221 GHK/PDV

PC CARD CONTROLLERS

SCPS042 – JULY 1998

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

secondary status register

Bit

Name

Secondary status

Type

R/C

Default

Secondary status

Type:

Read only, read/clear (see individual bit descriptions)

Offset:

16h

Default:

0200h

Description: The secondary status register is compatible with the PCI-to-PCI bridge secondary status

very similar to the PCI status register (offset 06h); status bits are cleared by writing a 1.

Table 18. Secondary Status Register

BIT

SIGNAL

TYPE

FUNCTION

CBPARITY

R/C

Detected parity error. Bit 15 is set when a CardBus parity error is detected (either address or data).

CBSERR

R/C

Signaled system error. Bit 14 is set when CSERR is signaled by a CardBus card. The PCI1221 does not

assert CSERR.

CBMABORT

R/C

Received master abort. Bit 13 is set when a cycle initiated by the PCI1221 on the CardBus bus has been

terminated by a master abort.

REC_CBTA

R/C

Received target abort. Bit 12 is set when a cycle initiated by the PCI1221 on the CardBus bus is

terminated by a target abort.

SIG_CBTA

R/C

Signaled target abort. Bit 11 is set by the PCI1221 when it terminates a transaction on the CardBus bus

with a target abort.

10–9

CB_SPEED

CDEVSEL timing. These read-only bits encode the timing of CDEVSEL and are hardwired 01b,

indicating that the PCI1221 asserts CB_SPEED at a medium speed.

CB_DPAR

R/C

CardBus data parity error detected.

0 = The conditions for setting bit 8 have not been met.

1 = A data parity error occurred and the following conditions were met:

a. CPERR was asserted on the CardBus interface.

b. The PCI1221 was the bus master during the data parity error.

c. The parity error response bit is set in the bridge control.

CBFBB_CAP

Fast back-to-back capable. The PCI1221 cannot accept fast back-to-back transactions; thus, bit 7 is

hardwired to 0.

CB_UDF

User-definable feature support. The PCI1221 does not support the user-definable features; thus, bit 6

is hardwired to 0.

CB66MHZ

66-MHz capable. The PCI1221 CardBus interface operates at a maximum CCLK frequency of 33 MHz;

therefore, bit 5 is hardwired to 0.

4–0

RSVD

Reserved. Bits 4–0 return 0s when read.

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