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HC210 데이터시트(PDF) 41 Page - Altera Corporation

부품명 HC210
상세설명  HardCopy II Device Family
PDF  228 Pages
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제조업체  ALTERA [Altera Corporation]
홈페이지  http://www.altera.com
Logo ALTERA - Altera Corporation

HC210 데이터시트(HTML) 41 Page - Altera Corporation

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Altera Corporation
3–5
September 2008
Preliminary
Document Revision History
f
For more information on JTAG or boundary-scan testing, refer to AN 39:
IEEE Std. 1149.1 (JTAG) Boundary-Scan Testing in Altera Devices.
1
Like Stratix II FPGAs, HardCopy II devices support the
SignalTap® II embedded logic analyzer, which monitors design
operation over a period of time through the JTAG interface. The
SignalTap II logic analyzer is a useful feature during the FPGA
prototyping phase, but should be removed if not needed once
the design has been migrated to a HardCopy II device.
HardCopy II is a mask programmed device, and the Signal Tap
logic cannot be eliminated after the HardCopy II device is
fabricated.
Document
Revision History
Table 3–5 shows the revision history for this chapter.
tJPH
JTAG port hold time
5
ns
tJPCO
JTAG port clock to output
11
ns
tJPZX
JTAG port high impedance to
valid output
14
ns
tJPXZ
JTAG port valid output to high
impedance
14
ns
tJSSU
Capture register setup time
4
ns
tJSH
Capture register hold time
5
ns
Table 3–4. HardCopy II JTAG Timing Parameters and Values (Part 2 of 2)
Symbol
Parameter
Min
Max
Unit
Table 3–5. Document Revision History (Part 1 of 2)
Date and Document
Version
Changes Made
Summary of Changes
September 2008,
v2.4
Updated chapter number and metadata.
—
June 2007, v2.3
● Added resource information
● Figure 3–1 changes
● New section on Boundary-Scan Test (BST) on HardCopy
II devices.
—
December 2006
v2.2
● Minor updates for Quartus II 6.1.0 software version
● Added revision history
Updated for Quartus II 6.1
software version.
October 2005, v2.1
Updated graphics.
—



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