THMC50

REMOTE/LOCAL TEMPERATURE MONITOR AND

FAN CONTROLLER WITH SMBus INTERFACE

SLIS090 – JULY 1999

7

POST OFFICE BOX 655303

otherwise noted)

temperature-to-digital converter timing parameters: Remote_Diode+, Remote_Diode–

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

t(SAMPLE)

Temperature-to-digital acquisition sample rate

0.75

1

1.25

sa/s

reset function timing parameters: VCC3, VCC3AUX, MR, AUXRST, RST

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

t(RP)

RST and AUXRST pulse duration

See Figures 17–20

140

560

ms

t(VCC3RST)

VCC3 to RST delay

See Figures 17–20

20

µs

t(VCC3AUX1)

VCC3AUX to AUXRST delay

See Figures 17–20

20

µs

t(VCC3AUX2)

VCC3AUX to RST delay

See Figures 17–20

20

µs

t(MR)

MR input to RST delay

See Figures 17–20

0.5

µs

t(RST)

AUXRST input to RST delay

See Figures 17–20

0.5

µs

t(MRMIN)

MR input minimum pulse width

10

µs

t(AUXRSTMIN)

AUXRST input minimum pulse width

10

µs

t(GLITCH)

MR, AUXRST glitch immunity

100

ns

SMBus interface timing parameters: SCL, SDA

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

f(SCL)

SCL operating frequency

See Figure 1

10

100

kHz

t(BUF)

Bus free time between stop and start condition

See Figure 1

4.7

µs

t(HDSTA)

Hold time after (repeated) start condition. After this period,

the first clock is generated

See Figure 1

4

µs

t(SUSTA)

Repeated start condition setup time

See Figure 1

4.7

µs

t(SUSTO)

Stop condition setup time

See Figure 1

4

µs

t(HDDAT)

Data hold time

See Figure 1

300

ns

t(SUDAT)

Data setup time

See Figure 1

250

ns

t(LOW)

SCL clock low period

See Figure 1

4.7

µs

t(HIGH)

SCL clock high period

See Figure 1

4

50

µs

t(LOWSEXT)

Cumulative clock low extend time (slave device)

See Figure 1

25

ms

t(LOWMEXT)

Cumulative clock low extend time (master device)

See Figure 1

10

ms

tF

Clock/data fall time

See Figure 1

300

ns

tR

Clock/data rise time

See Figure 1

1000

ns

NOTES:

6. Typicals are at TJ = TA = 25°C with V(VCC3AUX) = 3.3 V and represent most likely parametric norm.

7. Timing specifications are tested at the TTL logic levels, VIL = 0.4 V for a falling edge and VIH = 2.4 V for a rising edge. The 3-state

output voltage is forced to 1.4 V.