TL16C554, TL16C554I

ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS165D – JANUARY 1994 – REVISED JULY 1998

1

POST OFFICE BOX 655303

Element

Plus Steering Logic

Receiver Is Buffered With 16-Byte FIFO to

Reduce the Number of Interrupts to CPU

Registers Eliminate Need for Precise

Synchronization Between the CPU and

Serial Data

Operation

Which Allow Division of Any Input

Generate an Internal 16

× Clock

Communication Bits (Start, Stop, and

Parity) to or From the Serial Data Stream

Receive, Line Status, and Data Set

Interrupts

Characteristics:

– 5-, 6-, 7-, or 8-Bit Characters

– Even-, Odd-, or No-Parity Bit

– 1-, 1 1/2-, or 2-Stop Bit Generation

– Baud Generation (DC to 1-Mbit Per

Second)

– Loopback Controls for Communications

Link Fault Isolation

– Break, Parity, Overrun, Framing Error

Simulation

DTR, RI, and DCD)

Capabilities for Bidirectional Data Bus and

Control Bus

description

The TL16C554 and the TL16C554I are enhanced quadruple versions of the TL16C550B asynchronous

communications element (ACE). Each channel performs serial-to-parallel conversion on data characters

received from peripheral devices or modems and parallel-to-serial conversion on data characters transmitted

by the CPU. The complete status of each channel of the quadruple ACE can be read at any time during functional

operation by the CPU. The information obtained includes the type and condition of the operation performed and

any error conditions encountered.

The TL16C554 and the TL16C554I quadruple ACE can be placed in an alternate FIFO mode, which activates

the internal FIFOs to allow 16 bytes (plus three bits of error data per byte in the receiver FIFO) to be stored in

both receive and transmit modes. To minimize system overhead and maximize system efficiency, all logic is on

the chip. Two terminal functions allow signaling of direct memory access (DMA) transfers. Each ACE includes

a programmable baud rate generator that can divide the timing reference clock input by a divisor between 1 and

The TL16C554 and the TL16C554I are available in a 68-pin plastic-leaded chip-carrier (PLCC) FN package and

in an 80-pin (TQFP) PN package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Copyright

© 1998, Texas Instruments Incorporated