TL16C554, TL16C554I

ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS165D – JANUARY 1994 – REVISED JULY 1998

16

POST OFFICE BOX 655303

PRINCIPLES OF OPERATION

accessible registers

The system programmer, using the CPU, has access to and control over any of the ACE registers that are

summarized in Table 1. These registers control ACE operations, receive data, and transmit data. Descriptions

of these registers follow Table 3.

Table 3. Summary of Accessible Registers

ADDRESS

REGISTER

REGISTER ADDRESS

ADDRESS

MNEMONIC

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

0

RBR

(read only)

Data Bit 7

(MSB)

Data Bit 6

Data Bit 5

Data

Bit 4

Data Bit 3

Data Bit 2

Data Bit 1

Data Bit 0

(LSB)

0

THR

(write only)

Data BIt 7

Data BIt 6

Data BIt 5

Data

BIt 4

Data BIt 3

Data BIt 2

Data BIt 1

Data BIt 0

0†

DLL

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

1†

DLM

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

1

IER

0

0

0

0

(EDSSI)

Enable

modem

status

interrupt

(ERLSI)

Enable

receiver

line status

interrupt

(ETBEI)

Enable

transmitter

holding

register

empty

interrupt

(ERBI)

Enable

received

data

available

interrupt

2

FCR

(write only)

Receiver

Trigger

(MSB)

Receiver

Trigger

(LSB)

Reserved

Reserved

DMA

mode

select

Transmit

FIFO reset

Receiver

FIFO reset

FIFO Enable

2

IIR

(read only)

FIFOs

Enabled‡

FIFOs

Enabled‡

0

0

Interrupt

ID Bit (3)‡

Interrupt ID

Bit (2)

Interrupt ID

Bit (1)

0 If interrupt

pending

3

LCR

(DLAB)

Divisor

latch

access bit

Set break

Stick parity

(EPS)

Even

parity

select

(PEN)

Parity

enable

(STB)

Number of

stop bits

(WLSB1)

Word length

select bit 1

(WLSB0)

Word length

select bit 0

4

MCR

0

0

0

Loop

OUT2

Enable

external

interrupt

(INT)

Reserved

(RTS)

Request to

send

(DTR) Data

terminal

ready

5

LSR

Error in

receiver

FIFO‡

(TEMT)

Transmitter

registers

empty

(THRE)

Transmitter

holding

register

empty

(BI)

Break

interrupt

(FE)

Framing

error

(PE)

Parity error

(OE)

Overrun

error

(DR)

Data ready

6

MSR

(DCD)

Data

carrier

detect

(RI)

Ring

indicator

(DSR)

Data set

ready

(CTS)

Clear to

send

(

∆DCD)

Delta data

carrier

detect

(TERI)

Trailing

edge ring

indicator

(

∆DSR)

Delta data

set ready

(

∆CTS)

Delta

clear to send

7

SCR

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

† DLAB = 1

‡ These bits are always 0 when FIFOs are disabled.