TMS320F241FN datasheet(49/66 Pages) TI

49 / 66 page

TMS320C242

DSP CONTROLLER

SPRS063B – DECEMBER 1997 – REVISED DECEMBER 1999

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

low-power mode timings

switching characteristics over recommended operating conditions [H = 0.5tc(CO)]†

(see Figure 19, Figure 20, and Figure 21)

PARAMETER

LOW-POWER MODES

MIN

TYP

MAX

UNIT

Delay time, CLKOUT switching to

IDLE1

LPM0

4+6t

td(WAKE-A)

Delay time, CLKOUT switching to

program execution resume

IDLE1

LPM0

4 + 6 tc(CO) 15 tc(CO)

td(IDLE-COH)

Delay time, Idle instruction exe-

cuted to CLKOUT high

IDLE2

LPM1

4tc(CO)

td(WAKE-OSC)

Delay time, wakeup interrupt

asserted to oscillator running

HALT

{PLL/OSC

}

LPM2

OSC start-up

and PLL lock

time

td(IDLE-OSC)

Delay time, Idle instruction exe-

cuted to oscillator power off

{PLL/OSC power down}

LPM2

4tc(CO)

µs

td(EX)

Delay time, reset vector executed

after RS high

36H

† Timings assume CLKOUT is set to output CPUCLK. CLKOUT is initialized to CPUCLK by power-on reset.

WAKE INT‡

CLKOUT

A0–A15

td(WAKE–A)

‡ WAKE INT can be any valid interrupt or RESET

Figure 19. IDLE1 Entry and Exit Timing – LPM0

td(WAKE–A)

td(IDLE–COH)

WAKE INT‡

CLKOUT

A0–A15

‡ WAKE INT can be any valid interrupt or RESET

Figure 20. IDLE2 Entry and Exit Timing – LPM1

td(EX)

td(IDLE–COH)

td(IDLE–OSC)

RESET

CLKOUT

A0–A15

td(WAKE–OSC)

Figure 21. HALT Mode – LPM2

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