TMS320F241FN datasheet(17/66 Pages) TI

17 / 66 page

TMS320C242

DSP CONTROLLER

SPRS063B – DECEMBER 1997 – REVISED DECEMBER 1999

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

hardware-generated interrupts (continued)

CPU

IACK

Bus

Addr

Bus

Data

PIVR & logic

PIRQR#

PIACK#

IRQ GEN

Level 6

IRQ GEN

Level 5

IRQ GEN

Level 4

IRQ GEN

Level 3

IRQ GEN

Level 2

IRQ GEN

Level 1

XINT2

XINT1

ADCINT

TXINT

RXINT

CAPINT3

CAPINT2

CAPINT1

TOFINT2

TUFINT2

TCINT2

TPINT2

TOFINT1

TUFINT1

TCINT1

TPINT1

CMP3INT

CMP2INT

CMP1INT

TXINT

RXINT

XINT2

XINT1

ADCINT

PDPINT

INT1

INT2

INT3

INT4

INT6

INT5

IMR

IFR

PIE

Peripheral Interrupt Requests

(PIRQs)

Figure 5. Peripheral Interrupt Expansion Block Diagram

interrupt hierarchy

The number of interrupt requests available is expanded by having two levels of hierarchy in the interrupt request

system. There are two levels of hierarchy in both the interrupt request/acknowledge hardware and in the

interrupt service routine software.

TMS320F241FN 데이터시트(PDF) 17 Page - Texas Instruments

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