TMS320F241FN datasheet(26/66 Pages) TI

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TMS320C242

DSP CONTROLLER

SPRS063B – DECEMBER 1997 – REVISED DECEMBER 1999

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

functional block diagram of the ’24x DSP CPU

Data Bus

OSCALE (0–7)

ACCL(16)

ACCH(16)

CALU(32)

MUX

ISCALE (0–16)

MUX

PREG(32)

Multiplier

TREG0(16)

MUX

B1 (256

× 16)

B2 (32

× 16)

DARAM

B0 (256

× 16)

DARAM

LSB

from

MUX

DP(9)

MUX

ARAU(16)

ARB(3)

ARP(3)

Program Bus

AR7(16)

AR6(16)

AR5(16)

AR3(16)

AR2(16)

AR1(16)

AR0(16)

Stack 8

× 16

MUX

XTAL1/

CLKIN

CLKOUT

XTAL2

XINT[1–2]

AR4(16)

Data/Prog

PSCALE (–6, 0, 1, 4)

Data

ROM

MUX

NPAR

PAR

MSTACK

Program Control

(PCTRL)

Memory Map

IMR (16)

IFR (16)

GREG (16)

NMI

NOTES: A. Symbol descriptions appear in Table 8 and Table 9.

B. For clarity, the data and program buses are shown as single buses although they include address and data bits.

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