Full Bridge DC Motor Driver

SPF7302

10

Figure 4. Open Load Detection

Figure 5. Delay to Open Load protection activation versus value of external

capacitor on the output pins

VBB

DI

VOUT1

DIAG

A

B

C

0.01

0.1

1

10

100

1000

0.001

0.01

0.1

1

Maximum

Typical

Capacitance of Filter Capacitor on VOUT1 (μF)

Open Load Detection Delay Time versus Output Filtering Capacitance

Minimum

Figure 3. Behavior of Current Limitation and Overcurrent Protection

function

6 A (typ.) Overcurrent

3A (typ.) Current Limit

3 μs (typ.)

Protection Function Operation

Current Limitation and Overcurrent Protection

The overcurrent limit is adapted to each DMOSFET, and is acti-

vated when the drain current reaches 3 A typical. After that, it is

followed by a 3 μs typical off-time, and then it restarts automati-

cally.

Overcurrent protection is activated when the drain current reaches

6 A typical within 3 μs, as shown in figure 3. It shuts down the

IC in a latch mode. Setting the DI pin to logic low level resets the

internal logic circuit and releases the latch.

DIAG Pin and Open Load Detection Behavior

Open load detection does not operate until after the output volt-

is detected, the DIAG signal goes high. The process of open load

detection is shown in figure 4:

A. During this period, UVLO is activated and DIAG stays low.

B. If a filtering capacitor is used at the outputs, it causes a delay

of open load detection. (Refer to figure 5 for the relationship of

the delay versus the filtering capacitor value.)

C. The open load detection period starts functioning. Raising DI

the DIAG signal. Therefore, the open load condition must be

checked before the time of that event.

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com