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MPC2F35L 데이터시트(PDF) 11 Page - Megawin Technology Co., Ltd

부품명 MPC2F35L
상세설명  Low-speed USB micro-controller
PDF  46 Pages
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제조업체  MEGAWIN [Megawin Technology Co., Ltd]
홈페이지  http://www.megawin.com.tw/megawin_EN/Index.asp
Logo MEGAWIN - Megawin Technology Co., Ltd

MPC2F35L 데이터시트(HTML) 11 Page - Megawin Technology Co., Ltd

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MEGAWIN
MPC2F35_USB Data Sheet
11
0201H
FCPU_SR
-
-
-
-
-
-
-
CKS
-
√
At the 6M Hz external crystal, the internal clock source of MPC2F35 is 3M Hz by the default value.
CKS: FCPU clock source select register. 0: FOSC/2 (default), 1:FOSC
Release halt mode enable flag
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R
W
0202H
RLH_EN
-
-
INT1
INT0
P3
TM0
USB
-
-
√
Programmer can select the interrupt sources to release the halt mode through this register.
0: Disable (default), 1: Enable
After setting RLH_EN register, once there is one interrupt to release the halt mode, the programmer can
check the corresponding bit of the IRQ_ST register to know which interrupt source to execute this
release process.
Timer
Timer 0
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R
W
00C5H
TM0
T7
T6
T5
T4
T3
T2
T1
T0
√
√
00C6H
TM0_CTL
-
STC
RL/S
-
-
TKI2
TKI1
TKI0
√
√
STC: Timer clock disable/enable. 0: Disable timer clock (default), 1: Enable timer clock
RL/S: Auto-reload disable/enable. 0: Enable auto-reload (default), 1: Disable auto-reload
TKI2
TKI1
TKI0
Timer 0 clock source (FTM0CK)
0
0
0
FOSC / 8
0
0
1
FOSC / 16
0
1
0
FOSC / 32
0
1
1
FOSC / 64
1
0
0
FOSC / 128
1
0
1
FOSC / 256
1
1
0
FOSC / 512
1
1
1
FOSC / 1024
When timer 0 is used, it starts to pre-load value to this down-counter by setting the STC bit in the
TM0_CTL SFR and its underflow frequency (FTM0_UV) of timer 0 can be calculated by the following
equation:
FTM0_UV = FTM0CK / (TM0+1),
where FTM0CK is selected by TKI2, TKI1 and TKI0
For example: if FOSC=6M Hz and TKI2=0, TKI1=1, TKI0=0, then FTM0CK= FOSC / 32



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