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STM32F101XC 데이터시트(PDF) 78 Page - STMicroelectronics

부품명 STM32F101XC
상세설명  High-density access line, ARM-based 32-bit MCU with 256 to 512 KB Flash, 9 timers, 1 ADC and 10 communication interfaces
PDF  106 Pages
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제조업체  STMICROELECTRONICS [STMicroelectronics]
홈페이지  http://www.st.com
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STM32F101XC 데이터시트(HTML) 78 Page - STMicroelectronics

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Electrical characteristics
STM32F101xC, STM32F101xD, STM32F101xE
78/106
Doc ID 14610 Rev 7
Output driving current
The GPIOs (general purpose input/outputs) can sink or source up to +/-8 mA, and sink
+20 mA (with a relaxed VOL).
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 5.2:
●
The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run
consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating
IVDD (see Table 8).
●
The sum of the currents sunk by all the I/Os on VSS plus the maximum Run
consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating
IVSS (see Table 8).
Output voltage levels
Unless otherwise specified, the parameters given in Table 46 are derived from tests
performed under ambient temperature and VDD supply voltage conditions summarized in
Table 10. All I/Os are CMOS and TTL compliant.
Table 46.
Output voltage characteristics
Symbol
Parameter
Conditions
Min
Max
Unit
VOL
(1)
1.
The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 8
and the sum of IIO (I/O ports and control pins) must not exceed IVSS.
Output Low level voltage for an I/O pin
when 8 pins are sunk at the same time
TTL port,
IIO = +8 mA,
2.7 V < VDD < 3.6 V
0.4
V
VOH
(2)
2.
The IIO current sourced by the device must always respect the absolute maximum rating specified in
Table 8 and the sum of IIO (I/O ports and control pins) must not exceed IVDD.
Output High level voltage for an I/O pin
when 8 pins are sourced at the same time
VDD–0.4
VOL
(1)
Output low level voltage for an I/O pin
when 8 pins are sunk at the same time
CMOS port
IIO = +8 mA
2.7 V < VDD < 3.6 V
0.4
V
VOH
(2)
Output high level voltage for an I/O pin
when 8 pins are sourced at the same time
2.4
VOL
(1)
Output low level voltage for an I/O pin
when 8 pins are sunk at the same time
IIO = +20 mA
(3)
2.7 V < VDD < 3.6 V
3.
Based on characterization data, not tested in production.
1.3
V
VOH
(2)
Output high level voltage for an I/O pin
when 8 pins are sourced at the same time
VDD–1.3
VOL
(1)
Output low level voltage for an I/O pin
when 8 pins are sunk at the same time
IIO = +6 mA
(3)
2 V < VDD < 2.7 V
0.4
V
VOH
(2)
Output high level voltage for an I/O pin
when 8 pins are sourced at the same time
VDD–0.4



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