ATmega165 datasheet(111/336 Pages) ATMEL

111 / 336 page

111

ATmega165/V

2573G–AVR–07/09

Timer/Counter Timing

Diagrams

The Timer/Counter is a synchronous design and the timer clock (clk

T1) is therefore

shown as a clock enable signal in the following figures. The figures include information

on when Interrupt Flags are set, and when the OCR1x Register is updated with the

OCR1x buffer value (only for modes utilizing double buffering). Figure 49 shows a timing

diagram for the setting of OCF1x.

Figure 49. Timer/Counter Timing Diagram, Setting of OCF1x, no Prescaling

Figure 50 shows the same timing data, but with the prescaler enabled.

Figure 50. Timer/Counter Timing Diagram, Setting of OCF1x, with Prescaler (f

clk_I/O/8)

Figure 51 shows the count sequence close to TOP in various modes. When using phase

and frequency correct PWM mode the OCR1x Register is updated at BOTTOM. The

timing diagrams will be the same, but TOP should be replaced by BOTTOM, TOP-1 by

BOTTOM+1 and so on. The same renaming applies for modes that set the TOV1 Flag

at BOTTOM.

clk

(clk

I/O/1)

OCFnx

clk

I/O

OCRnx

TCNTn

OCRnx Value

OCRnx - 1

OCRnx

OCRnx + 1

OCRnx + 2

OCFnx

OCRnx

TCNTn

OCRnx Value

OCRnx - 1

OCRnx

OCRnx + 1

OCRnx + 2

clk

I/O

clk

(clk

I/O/8)

ATmega165 데이터시트(PDF) 111 Page - ATMEL Corporation

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