ATmega165 datasheet(113/336 Pages) ATMEL

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113

ATmega165/V

2573G–AVR–07/09

16-bit Timer/Counter

Timer/Counter1 Control

• Bit 7:6 – COM1A1:0: Compare Output Mode for Unit A

• Bit 5:4 – COM1B1:0: Compare Output Mode for Unit B

The COM1A1:0 and COM1B1:0 control the Output Compare pins (OC1A and OC1B

respectively) behavior. If one or both of the COM1A1:0 bits are written to one, the OC1A

output overrides the normal port functionality of the I/O pin it is connected to. If one or

both of the COM1B1:0 bit are written to one, the OC1B output overrides the normal port

functionality of the I/O pin it is connected to. However, note that the Data Direction Reg-

ister (DDR) bit corresponding to the OC1A or OC1B pin must be set in order to enable

the output driver.

When the OC1A or OC1B is connected to the pin, the function of the COM1x1:0 bits is

dependent of the WGM13:0 bits setting. Table 48 shows the COM1x1:0 bit functionality

when the WGM13:0 bits are set to a Normal or a CTC mode (non-PWM).

Table 49 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to the

fast PWM mode.

Bit

321

COM1A1

COM1A0

COM1B1

COM1B0

–

WGM11

WGM10

TCCR1A

Read/Write

R/W

Initial Value

Table 48. Compare Output Mode, non-PWM

COM1A1/COM1B1

COM1A0/COM1B0

Description

Normal port operation, OC1A/OC1B

disconnected.

Toggle OC1A/OC1B on Compare Match.

Clear OC1A/OC1B on Compare Match (Set

output to low level).

Set OC1A/OC1B on Compare Match (Set output

to high level).

Table 49. Compare Output Mode, Fast PWM

(1)

COM1A1/COM1B1

COM1A0/COM1B0

Description

Normal port operation, OC1A/OC1B

disconnected.

WGM13:0 = 14 or 15: Toggle OC1A on Compare

Match, OC1B disconnected (normal port

operation). For all other WGM1 settings, normal

port operation, OC1A/OC1B disconnected.

Clear OC1A/OC1B on Compare Match, set

OC1A/OC1B at BOTTOM (non-inverting mode)

Set OC1A/OC1B on Compare Match, clear

OC1A/OC1B at BOTTOM (inverting mode)

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